MESS Git (2015/09/25) is compiled. MESS(Multi Emulator Super System) is an open source emulator which emulates a large variety of different systems. MESS is a source-available project which documents the hardware for a wide variety of (mostly vintage) computers, video game consoles, and calculators through software emulation, as MAME does for arcade games. As a nice side effect to this documentation, MESS allows software and games for these hardware platforms to be run on modern PCs.

MESS Git Changelog:
* Merge pull request #341 from Wolf-Fivousix/master
Slight speedup to device_scheduler::timeslice(); JSMESS cleanups
* Code enhancement
Removed the assingment step by initializing target object with the value intended.
* Merge pull request #1 from Wolf-Fivousix/Wolf-Fivousix-patch-1
Code enhancement
* Code enhancement
No real need for an extra pointer here (device_scheduler * scheduler), only makes the code more cryptic.
Removed the assignment step by initializing the object with the value intended.
* gb.c: Added supergb2. (nw)
* Moved bus\a8sio files to bus\a800 to avoid redundancy (nw)
* Merge pull request #337 from JoakimLarsson/mvme350_2
MVME350 driver - Streaming Tape Controller support QIC-02
* Rebased to upstream HEAD
* cleaning up and adding some historical info about the boards origin
* Added color info of LEDs in PCB overview
* Improved address map and filled the PCB outline
* System ROM up and running, ROM/RAM adress map ok, started to add PIT
* started work on Motorola MVME-350
* cleaning up and adding some historical info about the boards origin
* Added color info of LEDs in PCB overview
* Improved address map and filled the PCB outline
* System ROM up and running, ROM/RAM adress map ok, started to add PIT
* started work on Motorola MVME-350
* Merge pull request #339 from Happy-yappH/master
n64.c: N64 changes: [Happy]
* PI transfers round down/truncate the last bit.
* SI transfers signal busy while waiting for a delay.
* Preliminary work for separating VI and RDP functionality.
* N64 changes
PI transfers round down/truncate last bit
SI transfers signal busy while waiting for delay
Initial work to seperate VI from RDP as the actual hardware has no direct communication between them
Stop ERET instruction spamming the error log
Stop screen update from spamming the error log for using MCFG_SCREEN_VBLANK_TIME. The value set was also complete nonsense.

Download: MESS Git (2015/09/25) x86
Download: MESS Git (2015/09/25) x64
Source: Here