Cen64 Git (2015/01/08) is compiled. Cen64 is a Cycle-Accurate Nintendo 64 Simulator.

Cen64 Git Changelog:
* Add (unoptimized) SSE2 support.
* Fix name mismatches of 'srcp' parameter in rsp_vect_load_and_shuffle_operand.
Signed-off-by: Tyler Stachecki
* Fix dereferencing of 'word' parameter in write_dd_regs.
Signed-off-by: Tyler Stachecki
* Fix a batch of mistakes in the last commit.
* Prevent 64DD thread from crashing.
RTC adjustment works and communication between the 64DD is
now present, but we don't actually save the RTC settings.
* Start filling in lots of 64DD implementation.
Also, fix a few bugs in the past two commits.
* Add C2, data sector and MS RAM mappings for 64DD.
* Add 64DD mappings and a controller.
* Decoder optimization: drastically reduce size.
* Remove an old, unused function.
* Perform some really clever branch folding.
Fold all the integer loads and stores into one code path.
* Trim off a few hundred bytes of code.
* Change the device subsystem cycle order.
We can eek out a little more performance by preferentially
cycles devices in a certain order.
* Same as the last commit, but with the RSP.
* Mark LDI (interlocks) as unlikely.
MIPS compilers of the time optimized this out very aggressively as
they waste cycles and there's generally other instructions you can
toss in the load delay slot, so flag the interlock as unlikely.
* Prevent a if statement over ternary expressions.
* Make interrupt exception checks more efficient.
* Fix a last-minute bug in TLB exceptions.
* Add support for TLB modification exceptions.
* Implement cache operations, fix cache op bug.
If we're doing a cache operation in the DC stage, don't
change the stage of the lines; the cache operations will
do it if needed. Also implement get/set taglo for DC.
* Respect the TLB entry conherency bits.
If the TLB entry 'C bits' indicate the cache isn't to be
used for that virtual address range... don't use the cache.
* Move cache functionality to the DC stage.
This is how the actual processor does it. In addition to
design correctness, we have the added benefit of being able
to support cache instructions whose virtual address lies
in a mapped part of the address space.
* More cleanup of the fault/TLB code.
* Temporarily patch the "render half frame" bug.
Not sure why copy_size should = 4 for a 16-bit frame, so
look into that. But for now, it won't cause any buffer
overruns, so enable it with a warning.
* Fix the JALR RSP bug, similar to last commit.
* Fix bugs, implement WatchLo/Hi support.
* Squash IC->RF latch data on a fault.
* Cleanup the VR4300 exception logic somewhat.
* Remove old function definitions.
* Merge more functions together.
* Merge a handful of the vector compares.
* Start merging RSP vector functions.
No need to separate all these functions when they contain so
much common code, so start combining things for the sake of
locality and predictor effectiveness (and size). In addition
to these benefits, the CPU backend is usually busy during the
execution of these functions, so suffering a misprediction
isn't as painful (especially seeing as we can potentially
improve the prediction from the indirect branch).
* Disable register caching for now.
Until we can work around system libraries stomping over the
registers we want to reserve, just disable register caching for
the time being.
* Add an implementation for VMACU.
* Fix VMACF accumulation issues and lighting problems.
* Hacky fix to patch register caching.
On Windows, acc_lo (%xmm5) was clashing with the x64 calling
convention, which states %xmm5 is a volatile register and is
the caller's responsibility to save. We need the register
preserved across calls, so until we have a better solution to
the problem, pick registers that are not volatile according to
the calling convention.
* Fix a CFC2/VCE error that produced the wrong mask.
* Fix potential undefined behaviour issues.
* Fix a series of RSP bugs that krom pointed out.
* Add support for building on OS X.
* Add a missing line to CMakeLists.txt.
* Restore most TLB functionality from backport.
* Update README and prepare for GitHub push.
* Don't boot when if the CIC type is not known.
* Automatically seed the PIF RAM based on CIC type.
* os/windows: Only show the console when asked.
* Clean up some rough edges in the last commit.
* Get the Windows build in running condition.
Conflicts:
rdp/n64video.c
* os/unix: Shuffle things around to align with WINAPI.
* Commit some MSVC-specific workarounds.
* Fix VLT clipping bugs.
Thank you, AIO, for pointing this out.

Download: Cen64 Git (2015/01/08)
Source: Here